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2.4GHz DSSS SPI Radio for External Antenna
AWS24S
Data Sheet
The SPI communications interface has a burst mechanism, where the first byte can be followed by as many data bytes as
desired. A burst transaction is terminated by deasserting the slave select (
= 1).
The SPI communications interface single read and burst read sequences are shown in Figure 3 and Figure 4, respectively.
The SPI communications interface single write and burst write sequences are shown in Figure 5 and Figure 6, respectively.
This interface may optionally be operated in a 3-pin mode with the MISO and MOSI functions combined in a single
bidirectional data pin (SDAT). When using 3-pin mode, user firmware should ensure that the MOSI pin on the MCU is in a
high impedance state except when MOSI is actively transmitting data.
The device registers may be written to or read from 1 byte at a time, or several sequential register locations may be
written/read in a single SPI transaction using incrementing burst mode. In addition to single byte configuration registers, the
device includes register files; register files are FIFOs written to and read from using non-incrementing burst SPI transactions.
The IRQ pin function may optionally be multiplexed onto the MOSI pin; when this option is enabled the IRQ function is not
available while the
pin is low. When using this configuration, user firmware should ensure that the MOSI pin on the
AWS24S is in a high impedance state whenever the
pin is high.
The SPI interface is not dependent on the internal 12-MHz clock, and registers may therefore be read from or written to while
the device is in sleep mode, and the 12-MHz oscillator disabled.
Figure 2 – SPI Transaction Format
Figure 3 - SPI Single Read Sequence
Figure 4 - SPI Incrementing Burst Read Sequence
Figure 5 - SPI Single Write Sequence
Artaflex Inc.
215 Konrad Crescent
Markham, Ontario, Canada
DSAWS24S Rev 5v0
Revised Jan 23, 2009
L3R8T9
905-479-0148
Page 5 of 14
http://www.artaflexmodules.com
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